In the signal processing field, pipelined AD converters are used. The pipelined AD converter includes a plurality of cascaded conversion stages, and in each of the conversion stages, analog-to-digital conversion and amplification/output of a residual voltage are sequentially executed, to convert an analog signal to a digital signal bit by bit.
In general, in the pipelined AD converter, higher amplification precision is required for a conversion stage closer to the first conversion stage. For example, in a pipelined AD converter for converting an analog input voltage to 10-bit digital data, while the tolerable error (tolerance) for the final (tenth) conversion stage is “(½) times as large as the input voltage,” the tolerance for the ninth conversion stage is “(½)2 times as large as the input voltage,” and the tolerance for the first conversion stage is “(½)10 times as large as the input voltage.” That is, the tolerance decreases by (½) every stage from the final conversion stage toward the first conversion stage. Also, it is preferred to reduce the circuit scale and power consumption of the pipelined AD converter. For these reasons, the individual conversion stages are designed so that the capacitance value of capacitors, the gain of operational amplifiers (op-amps), and the current drive capability of the op-amps decrease in the order from the first conversion stage toward the final conversion stage. With this, the amplification precision becomes higher for a conversion stage closer to the first conversion stage, and the circuit scale and the power consumption become smaller for a conversion stage closer to the final conversion stage. In this way, conventionally, capacitors and op-amps are optimally designed for each conversion stage (see Non-Patent Document 1, for example).
Also, in recent years, analog circuits have been increasingly downsized, and hence it has become difficult to correct an output error in an analog circuit under an analog configuration. For this reason, digital correction techniques have been vigorously developed in which the output error in an analog circuit is determined in advance and digital data is corrected so as to solve the output error (see Patent Document 1, for example).
Non-Patent Document 1: M. Miyahara, T. Kurashina, A. Matsuzawa, “A study on the effect of CMOS scaling in the analog circuit performance—The effect of design rule on CMOS Op-amps and pipeline ADCs,” The Institute of Electronics, Information and Communication Engineers, Technical Committee on Integrated Circuits and Devices (ICD), Toyohashi, ICD2005-59, Vol. 105, No. 185, pp. 25-30, July 2005Patent Document 1: U.S. Pat. No. 6,545,628